1. Field of Use
The present invention relates to data processing systems having memory systems which include a high speed buffer store or cache unit.
2. Prior Art
It is well known that many data processing systems each include a main memory or main store and high speed low capacity buffer store or cache, each of which is positioned between the system's data processing unit and its main memory. In such systems, an associative memory normally is used to store the block addresses for indicating which blocks are stored or reside in the cache or buffer store. When a fetch or read request occurs, the associative memory is interrogated to determine whether the block containing the addressed word resides in cache. If not, the word together with associated words of a block are fetched from main store and read into cache or buffer store.
Generally recognized are the cost advantages of having the cache or buffer store contain a limited number of blocks to minimize the size of associative memory. However, others have recognized certain disadvantages resulting from such storage limitations in the case of block transfers. In overcoming such disadvantages, one high speed memory system provides a high degree of overlap or concurrency wherein additional accesses to the memory system may be executed after a block transfer has been initiated. U.S. Pat. No. 3,588,829 is an example of one such system.
In providing such overlap, it is possible to receive more than one request specifying fetching data from the same block. To avoid the generation of multiple commands to main memory or backing store, additional comparison circuits or associative memory circuits together with a multiplicity of control bits are included to detect conflicting requests. During additional cycles, comparisons are made and the results are stored to be used to control the fetching of commands. Such arrangements have found to result in increased cost and complexity. Moreover, such arrangements are unable to process a variety of different types of commands which give rise to increases of overlap.
Accordingly, it is a primary object of the present invention to provide a buffer store or cache arrangement which permits a high degree of overlap with minimal increases in cost and complexity.
It is a further object of the present invention to provide a low cost buffer store or cache capable of executing a variety of different types of memory commands without requiring the issuance of duplicate commands.